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Components for Satellite Receiver Units
DCR Sat-Frontend TUA6100B6 Gain controlled I/Q Mixer for digital QPSK Sat signals
Preliminary Specification 01.2001
V219
Edition 01.2001 Published by Infineon AG , Marketing-Communication, Balanstr. 73, 81541 Munich (c) Infineon AG 1999. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Office, Semiconductor Group. Infineon AG iGr is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Infineon AG iGr, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Infineon AG iGr. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
Ausgabe 01.2001 Herausgegeben von Infineon AG , Marketing-Kommunikation, Balanstrae 73, 81541 Munchen (c) Infineon AG 1999. Alle Rechte vorbehalten. Wichtige Hinweise! Gewahr fur die Freiheit von Rechten Dritter leisten wir nur fur Bauelemente selbst, nicht fur Anwendungen, Verfahren und fur die in Bauelementen oder Baugruppen realisierten Schaltungen. Mit den Angaben werden die Bauelemente spezifiziert, nicht Eigenschaften zugesichert. Liefermoglichkeiten und technische Anderungen vorbehalten. Fragen uber Technik, Preise und Liefermoglichkeiten richten Sie bitte an den Ihnen nachstgelegenen Vertrieb Halbleiter in Deutschland oder an unsere Landesgesellschaften im Ausland. Bauelemente konnen aufgrund technischer Erfordernisse Gefahrstoffe enthalten. Auskunfte daruber bitten wir unter Angabe des betreffenden Typs ebenfalls uber den Vertrieb Halbleiter einzuholen. Die Infineon AG iGr ist ein Hersteller von CECC-qualifizierten Produkten. Verpackung Bitte benutzen Sie die Ihnen bekannten Verwerter. Wir helfen Ihnen auch weiter - wenden Sie sich an Ihren fur Sie zustandigen Vertrieb Halbleiter. Nach Rucksprache nehmen wir Verpackungsmaterial sortiert zuruck. Die Transportkosten mussen Sie tragen. Fur Verpackungsmaterial, das unsortiert an uns zuruckgeliefert wird oder fur das wir keine Rucknahmepflicht haben, mussen wir Ihnen die anfallenden Kosten in Rechnung stellen. Bausteine in lebenserhaltenden Geraten oder Systemen mussen ausdrucklich dafur zugelassen sein! Kritische Bauelemente1 des Bereichs Halbleiter der Infineon AG iGr durfen nur mit ausdrucklicher schriftlicher Genehmigung des Bereichs Halbleiter der Infineon AG iGr in lebenserhaltenden Geraten oder Systemen2 eingesetzt werden. 1 Ein kritisches Bauelement ist ein in einem lebenserhaltenden Gerat oder System eingesetztes Bauelement, bei dessen Ausfall berechtigter Grund zur Annahme besteht, da das lebenserhaltende Gerat oder System ausfallt bzw. dessen Sicherheit oder Wirksamkeit beeintrachtigt wird. 2 Lebenserhaltende Gerate und Systeme sind (a) zur chirurgischen Einpflanzung in den menschlichen Korper gedacht, oder (b) unterstutzen bzw. erhalten das menschliche Leben. Sollten sie ausfallen, besteht berechtigter Grund zur Annahme, da die Gesundheit des Anwenders gefahrdet werden kann.
TUA6100B6 Revision History:Current Version: 01.2001 , V219 Previous version:10.2000 , V217 -> V218 old Page cover cover cover 20 22 22 22 22 22 22 22 23 23 23 23 23 27 27 28 new Page cover cover cover 20 22 22 22 22 22 22 22 23 23 23 23 23 27 28 29 Subjects (major changes since last revision) copper lead frame removed Edition date Spec version Hysteresis of Schmitt trigger inputs, new ESD note, updated Ambient temperature, updated Thermal resistance P-TSSOP28 + PCB board, removed Detailed description of the needed thermal resistance, removed Air gap package tolerances, removed Thermal resistance junction case, new Detailed description of the maximum junction temperature , new RF input (950-2150MHz) section, definition changed to symm. balanced input, referenced to test circuit Input RF level min. value corrected, test condition changed Input gain control range, test condition changed Quadrature error, phase + gain, test condition added Quadrature error, gain, value corrected Test circuit , new Application circuits , updated input configuration Application circuits , updated input configuration + crystal series capacitor
Previous version:12.2000 , V218 old Page cover cover 2 22 23 23 27, 28 41 new Page cover cover 2 22 23 23 28, 29 41 Subjects (major changes since last revision) Edition date Spec version Ordering Information, packages updated Ambient temperature note, updated Minimum input RF level , new description Maximum input RF level , new description Application circuits , updated input configuration Plastic Package, P-TSSOP-28-1 alloy leadframe, added
Data Classification Maximum Ratings Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Characteristics The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and the given supply voltage. Operating Range In the operating range the functions given in the circuit description are fulfilled. For detailed technical information about "Processing Guidelines" and "Quality Assurance" for ICs, see our "Product Overview".
TUA6100B6
Table of Contents
Page
1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 3 4 5 6 7 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.11.1 8.11.2 8.11.3 8.12 8.12.1
General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Input Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Baseband Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Output Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Reference Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Reference Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Crystal Oscillator Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Synthesizer Loop filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Synthesizer VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Phase Shift 0 / 90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 GHz VCO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 GHz PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional GHz PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 GHz PLL programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Synthesizer VCO band switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Synthesizer PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Serial Bus Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 I2C bus mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3-wire bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Dual Modulus Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 R-Counter and A- / N-Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Phase Comparator (Frequency/Phase Detector). . . . . . . . . . . . . . . . . . . . . . . . . . 11 Charge Pump. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Lock Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Functional Synthesizer PLL Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Divide ratio programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Phase detector outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Chipaddress Organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Subaddress Organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bus Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Data Byte Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
i 26.1.01
8.12.2 8.12.3 8.12.4 8.13 8.13.1 8.13.2 8.13.3 8.13.4 8.13.5
High-Frequency-Products
Preliminary Specification
TUA6100B6
9 9.1 9.2 9.3 10 11
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 AC/DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 high side synthesizer VCO narrow band loop filter example . . . . . . . . . . . . . . . . . 28 high side synthesizer VCO wide band loop filter example . . . . . . . . . . . . . . . . . . . 29 Phase noise performance of application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Optimum phase detector current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 VCO steepness + phase detector current ranges . . . . . . . . . . . . . . . . . . . . . . . . . 31 VCO tuning voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Receiving frequency band splitting into 2 or 3 ranges . . . . . . . . . . . . . . . . . . . . . . 32 Base band filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Frequency response incl. the two base band amplifiers + output load . . . . . . . . . 33 Group delay incl. the two +16 dB base band amplifiers + output load. . . . . . . . . . 33 Electrical Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Frequency flatness of base band outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Group delay of base band outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Frequency response of base band outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Group delay at low frequencies, dependent on coupling capacitor . . . . . . . . . . . . 36 RF gain control range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 RF input impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 RF input impedance continued, Smith diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Base band output impedance pin 13, 14 (filtered), Smith diagram . . . . . . . . . . . . 38 Base band output impedance pin 19, 20 , Smith diagram . . . . . . . . . . . . . . . . . . . 39 Base band output impedance Pin 19, 20 (Ohm) . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Base band output inductance Pin 19, 20 (Henry) . . . . . . . . . . . . . . . . . . . . . . . . . 40 Base band Input Impedance (filtered) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
12
13 13.1 13.2 13.3 13.4 13.5 13.6 13.7
13.8 14
High-Frequency-Products
ii
26.1.01
DCR Sat-Frontend Gain controlled I/Q Mixer for digital QPSK Sat signals
Preliminary Specification
TUA6100B6
BICMOS
1

Features
Low impedance gain controlled RF input Dual matched double balanced mixer Digital generation of 0/90 LO signal Direct down conversion from 1. IF (LNB output) to base band 0-30 MHz IF filter not necessary I / O for external baseband filter CMOS PLL-Synthesizer Active loop filter (high voltage) 3 high current switch outputs Buffered crystal oscillator output Low noise reference voltage 3-wire bus and I2C bus with 4 addresses + subaddresses Splitting of Sat tuning range into 2/3 bands LO - frequency below and above input frequency possible
TSSOP-28
Package
2
General Description
The TUA 6100 is a low cost chip in the newest Infineon high speed BICMOS technology B6HFC. It is designed to implement the direct conversion receiver principle for digital QPSK-Sat receiving systems. The DCR architecture eliminates the need for expensive RF-Filters for image rejection and IF-Frequencies for channel selection. Instead, an inexpensive base band low-pass filter is used for channel selection, and no image rejection filter is required. These base band filter enable the possibility for an on chip integration. (not part of TUA6100) The DCR system is the most promising architecture to lower the cost of digital set-top boxes front end. Via a gain controlled RF preamplifier (not part of TUA6100) with approx. 30 dB gain and some selectivity, the RF signal is symmetrical fed to two low input impedance double balanced mixers . The mixers have common inputs with internal power splitting and incorporate a new patented direct gain control in the mixer input stage and an additional gain control at the mixer output to improve S/N ratio. The signal of the synthesizer tuning VCO is multiplied to 4 x RF input frequency via a complete internal 3.8-8.6 GHz PLL system. To drive the mixers, this 3.8-8.6 GHz signal is split into quadrature components by a Johnson-counter . The mixers are followed by 2 matched 16 dB fixed gain base band amplifiers making available the first linear DC-coupled base band outputs with approx. 224 mVpp for the I and Q signal . Two additional 16 dB fixed gain base band amplifiers with approx. 1 Vpp output voltage enable the possibility to use system adapted external AC-coupled base band filter and eliminate undesirable DC-components of the first amplifiers . High-Frequency-Products 1 26.1.01
Preliminary Specification
TUA6100B6
The TUA 6100 contains - 2 double balanced mixer cells with new patented direct gain control, - a digital generation of the 0/90 local oscillator phase shifted signal to ensure minimum quadrature phase error, - an internal synthesizer VCO with programmed band splitting and external varactor and resonator, - 2 internal GHz VCO's and a PLL for generation of 4 x RF input frequency, (necessary for the accurate digital generation of the LO I/Q components) - a CMOS PLL-synthesizer controlled by I2C or 3-wire bus, - an active synthesizer loopfilter with high voltage and high current output, - an on chip reference oscillator (external crystal) which can be overridden by an external oscillator, and - 4 ultra linear base band output amplifiers with approx. 16dB gain each. The PLL-synthesizer is programmable to work with reference frequencies > 4kHz and up to 2 MHz, for more information see Divide ratio programming on page 14. A programmable phase detector output current makes it easy to select several transconductances controlled by bus. A simple Windows control-program for I2C / 3-wire bus with short description is available.
3
Type
Ordering Information
Ordering Code Q 67037-A 1034 A 701 not yet available Package P-TSSOP-28-1 P-TSSOP-28-5
TUA6100B6 TUA6100B6
4
Pin Configuration
top view
2-pin synthesizer VCO configuration
QOSZ VCC PDLOOP TUNE GND P1 OB1 OB2 P2 PDOUT BUSMODE GND1 IFOUT QFOUT
1 2 3 4 28 27 26 25
Xtalout SDA SCL CAS P0 RFINY RFINX GAIN QOUT IOUT VCC1 IFIN GND2 QFIN
6 7 8 9 10 11 12 13 14
P-TSSOP-28-1
2
5
24 23 22 21 20 19 18 17 16 15
High-Frequency-Products
26.1.01
Preliminary Specification
TUA6100B6
5
Pin Definitions and Functions
Pin No. Symbol QOSZ VCC PDLOOP TUNE GND P1 OB1 OB2 P2 PDOUT BUSMODE GND1 IFOUT QFOUT QFIN GND2 IFIN VCC1 IOUT QOUT GAIN RFINX RFINY P0 CAS SCL SDA Xtalout Function Reference oscillator input / Crystal Power supply voltage for I2C / 3-wire bus and synthesizer Synthesizer Phase detector Charge pump output / Loop filter input Synthesizer Loop filter high voltage tuning output Ground for I2C / 3-wire bus and synthesizer Port 1 output VCO for synthesizer, stripline input 1 VCO for synthesizer, stripline input 2 Port 2 output Phase detector loop filter of internal GHz-PLL Selection of I2C / 3-wire bus Ground for analog part; LO and 0/90 phase generator Base band I output Base band Q output Q baseband filtered input signal Base band Ground I baseband filtered input signal Power supply voltage for analog part; LO and 0/90phase generator Base band I output for base band filter Baseband Q output for baseband filter AGC voltage input RF differential input signal (950-2150MHz) Port 0 output CAS input for I2C bus, Enable input for 3-Wire-bus Clock input for I2C bus, Clock input for 3-Wire-bus SDA input/output for I2C bus, Data input for 3-Wire-bus Buffered crystal oscillator output
P-TSSOP-28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
6

Applications
DBS, DVB-S, DSS Set-Top Boxes, any I/Q Downconverter from 950 MHz - 2150 MHz to frequencies 0 - 30 MHz
High-Frequency-Products
3
26.1.01
High-Frequency-Products 4 26.1.01
7 Block Diagram
Bus Control
Xtalout 28 SDA 27 Clock 26 CAS 25
Port
P0 24
-55...-15 dBm @ 50 symm.
RFinY 23 RFinX 22 GAIN 21 20
- 9 dBm 30 MHz
Qout Iout 19 VCC1 18 IFin 17
Basebandfilter
Gnd2 16 QFin 15
digital power supply
Buffer
Ports
Dual I /Q Mixer
-10..30 dB Gain
Dual 16 dB Baseband Amplifier
Dual 16 dB Baseband Amplifier
Preliminary Specification
CMOS Synthesizer PLL
GHz Prescaler
GHz PLL (4 x Fin) Quadratur Phase Generator
Loop
Power Regulation
Tuning
Crystal Oscillator
Active Loopfilter
Synthesizer VCO Low Noise Bandgap
analog power supply
1 QOSZ
2 VCC
3 PDLOOP
4 TUNE
5 GND
6 P1
7 OB1
8 OB2
9 P2
10 PDout
11 Busmode
12 Gnd1
13 IFout
14
TUA6100B6
QFout
Crystal
2 kHz Loopfilter
Tank Circuit
9 MHz Loopfilter
+ 4 dBm output
Preliminary Specification
TUA6100B6
8
Circuit Description
The main function of the chip is split into bipolar analog signal processing, bipolar digital signal generation of 0/ 90 LO-signal and a CMOS synthesizer. Extremely symmetrical layout with matched structures promises best phase and gain balance of the inphase and quadraturephase signals.
8.1 Input Mixer
Parameter see RF input (950-2150MHz) symm. balanced signal on page 23 Main function is the conversion of a preselected satellite 1. IF band into the inphase and quadraturephase baseband signals. The input stage of the mixer is directly combined with a new patented differential input gain control of 30 dB control range and a double balanced mixer with additional gain control of 15 dB in the output. The integration of the gain control into the mixer cell results in high compression point / IP3 at full attenuation and requires low chip area . The differential input has low impedance and is designed for 50 systems with a certain mismatch. Due to the built in gain control the mixer conversion gain varies between -10 and +35 dB. The output is internal DC-coupled to the first base band amplifier. For best performance the 0/ 90 LO-signal is fed to the mixer via open collector stages with well defined output impedance and levels. The AGC voltage input is positive DC-controlled, that means 0.5V - min. gain, 3V - max. gain, with MOS high impedance input. The characteristic of the RF gain control range is mainly non linear .
8.2 Baseband Amplifier
Parameter see Base band I / Q output, on page 23 and Base band I / Q output filtered, on page 24 The 4 base band amplifiers are of wide-band operational type with high overshoot margin. The DC reference voltage is internal set to 2.15 V dc . All the amplifiers have a fixed gain of 16 dB and 30 MHz-0dB bandwidth. The distribution of the whole DC-gain into two AC-coupled 16 dB amplifiers ensures that the base band amplifiers are not overdriven by a large DC-voltage that may be caused by mixer offset or mixer LO feedback to the input. All 4 outputs can be disabled by bus control. (Register 02,D14) In this state the outputs switch to low voltage and low impedance.
8.3 Output Ports
Parameter see Port outputs, P0, P1, P2 on page 26 The output ports are designed with open collector transistor for high current pull down and slow switching application.
8.4 Reference Voltage
Parameter see Power supply on page 23 The central reference voltage is a low noise high PSSR bandgap with approx. 2.4 V DC and low temperature drift.
8.5 Reference Oscillator
Parameter see Reference oscillator input / Crystal on page 24 The reference oscillator input is the low impedance feedback of a cascode amplifier and uses the low series resonance of a crystal to generate an oscillation condition. For a wide characteristic range the reference oscillator can use crystals from 1 - 16 MHz and may be used as external AC-coupled reference input if no crystal is present.
High-Frequency-Products
5
26.1.01
Preliminary Specification
TUA6100B6
8.6 Crystal Oscillator Output
Parameter see Crystal oscillator output on page 26 To reduce the amount of application components in combination with a digital QPSK demodulator, the TUA 6100 offers an buffered Push-Pull output of the crystal oscillator. The frequency is the crystal frequency and is not programmable, the output signal is always on.
8.7 Synthesizer Loop filter
Parameter see Synthesizer Loop filter high voltage tuning output on page 25 The synthesizer active loop filter consists of a simple inverting BICMOS amplifier with MOS input and a special open collector output transistor which can handle high voltage and high output currents. The loop filter input is internal connected to the phase detector / charge pump output. The BICMOS amplifier output may be disabled (high Z) by bus, control register (Register 00,D0).
8.8 Synthesizer VCO
Parameter see Synthesizer VCO on page 26 . The synthesizer VCO is a symmetrical Colpitts type oscillator with an external tank circuit. The tank circuit consists of two microstrip lines connected to the oscillator bases and at the microstrip line ends two serial connected varicap diodes. These diodes are driven by the tuning voltage. The synthesizer VCO oscillates at a programmed offset to the input frequency. This guarantees minimum oscillator pulling and self-mixing with the result of undesirable DC-signal voltage. The offset may be at low side or high side of the input signal or zero (that means Fvco = Finput ). The VCO tuning range is digital split into 2 or 3 bands controlled by the internal GHz PLL. (not possible if operation Fvco = Finput is desired for the hole tuning range) Advantages : * only one optimized VCO for the complete tuning range which is approx. 1 : 2.34 (due to the KVCO and Loop bandwidth variation it is difficult to obtain this range by one conventional VCO with constant low phase noise) . * reduced external components * smaller package * lower phase noise due to the reduced tuning range of VCO * lower synthesizer loop filter bandwidth variation * lower maximum tuning voltage. Detailed programming tables see GHz PLL programming on page 9 .
8.9 Phase Shift 0 / 90
Parameter see Synthesizer PLL on page 25 To get minimum quadrature phase error, a digital generation of the 0/90 phase shifted local oscillator signal is implemented by a 3.8-8.6 GHz Johnson-counter This counter is designed in high speed stacked ECL bipolar technology.
8.10 GHz VCO
Two On-Chip bipolar LC-Oscillators (3.4-6.2 GHz and 6.0-8.6 GHz) controlled via On-Chip PLL . The GHz VCO's oscillate at 4 x of the input frequency and are current controlled. The resonant circuit is an on chip symmetrical inductor driven by differential pair amplifier whose current variable parasitic capacitance is used for frequency tuning. The used special multi-tanh gilbert cell makes a wide tuning range possible. The complete GHz VCO's are under control of a 3.8-8.6 GHz PLL system. The reference frequency of this system is the output of the synthesizer VCO divided by a programmable counter; variation is 118-538 MHz(depending on the selected synthesizer tuning range). At the same time this is the operating frequency range of the phase detector / charge pump. The high speed charge pump is completely on chip and designed in BICMOS technology with an external loop filter bandwidth set to 9 MHz. The GHz VCO frequency is fed to the phase detector via the high speed ECL Johnson counter 4 and a lower speed programmable ECL counter. High-Frequency-Products 6

26.1.01
Preliminary Specification
TUA6100B6
8.11 GHz PLL
Normally in DCR systems it is necessary that the synthesizer VCO oscillates exact at the desired receiving frequency. The following description shows a new patent pending double PLL tuning system without this requirement and enables some features that other concepts do not have. The main benefit of this new concept is : - - - - - the accurate 0 / 90 generation of the LO signals for the RF input mixer, no oscillator on input frequency, a programmed frequency offset of synthesizer VCO to the RF input frequency and due to that a very low VCO oscillator pulling and self mixing according to power crosstalk of RF input and the possibility of splitting the tuning range into bands. Responsible for these advantages is a 2nd GHz PLL system with two VCO's at 4 x Fin. This 2nd GHz PLL system is located in the broken up feedback of the synthesizer PLL 1 between the VCO1 and the programmable counter input N1. This represents a system of two cascaded PLL's.
Fref PLL 1 (Synthesizer) PLL 2
VCO1
VCO2
R1
PD1
CP1
interrupted PLL 1
R2
PD2
CP2
N : main counter N1 R : reference counter PD : phase detector CP : charge pump VCO : voltage controlled oscillator Q2 : Quadraturphase + prescaler
X
N2
Q2
cascaded PLL system
LO I/Q output to mixer
This location enables a shift of the synthesizer VCO1 to other frequencies, independent of the required input LO frequency of the RF mixers. In this case the synthesizer VCO must not oscillate at the required LO frequency of the mixer input. Nevertheless the synthesizer PLL is referenced to the LO frequency of the mixer input which makes it easy to program the PLL because it is set exact to the receiving frequency. Another benefit is the exact mapping of the PLL stepsize to the tuning frequency. This is not possible in a conventional PLL tuning system with the feedback of the VCO1 direct to the programmable counters N1, if the VCO1 is not running on the RF input frequency. This may become clear in the above concept, if the interrupted PLL 1 is closed and the LO I/Q output is cut off from node x. In this case step size and tuning frequency have additional terms of calculation. Depending on the system concept. they do not fit to the programmed values of the synthesizer PLL 1, because it is referenced to the VCO1 and no longer to the LO I/Q output. ( following dependencies will become valid, Ftune = (N2 / R2)Fvco1 and Fstep = (N2 / R2)PLL1step ). The R2 and N2 counters of the GHz PLL enable a programmable frequency offset of the synthesizer VCO to the RF input as well as a splitting of the required RF tuning range. For the band splitting feature the counters R2 and N2 of the GHz PLL must be used with 2 different values (e.g. 4/2 and 4/3). As a result VCO1 will pass his range twice, while the LO I/Q output to mixer will have a tuning range which is split into 2 bands.
In the feedback of the GHz PLL is located the high speed Johnson-counter prescaler for the two 3.4 - 8.6 GHz VCO's and accurate 0 / 90 LO generator.
(Q2) which acts as
The complete GHz PLL is designed in high speed ECL cascoded technology which enables counter frequencies up to 15 GHz , oscillator frequencies up to 10 GHz and phase detector / charge pump signal slopes of less then 100 ps.
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Preliminary Specification
TUA6100B6
8.11.1 Functional GHz PLL Block Diagram
2nd GHz PLL (Quadrature Phase loop)
loop filter 9 MHz programming lines
VCO2 4 x Fin 3.4-6.2GHz 6.0-8.6GHz
0.95-2.15
R2
programmable counter 2/3/4 counter 2 0.4 - 3.3 GHz
Fpd2
counter 2 0.9 - 2.2 GHz
2nd loop reference input
detailed
drawing
Fvco = FIQ R2 ----
N2
2nd GHz-PLL , performing Quadrature Phase Generator, Band splitting and VCO offset
Fvco
Synthesizer VCO 0.4 - 2.9 GHz reference oscillator 1-16 MHz programming lines input synthesizer input = Fpr Fvco conventional synthesizer loop
loop filter 2 kHz
I2C / 3-wire bus programming Interface
R
programmable counter 2-1023 0.5 - 16 MHz Fref phase detector type 4 DC - 2 MHz
N+A
programmable counter 2-2023 0.5 - 100 MHz FN
programming lines
Synthesizer Loop
High-Frequency-Products
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phase detector type 4 100-550 MHz
N2
programmable counter 2/3/4 counter2 0/90counter2
GHz to the mixer
I Q
2nd loop output
P
modulus.prescaler 32 / 33 ; 64 / 65 0.2 - 2.5 GHz
26.1.01
Preliminary Specification
TUA6100B6
8.11.2 GHz PLL programming
programmable tuning ranges of the synthesizer VCO controlled by GHz PLL for Fin = 950 - 2150 MHz
FVCO FInput
-----------------
0.5
2 -4
0.66
2 -3
0.75
3 -4
1
2 -2
1
3 -3
1
4 -4
1.33
4 -3
1.5
3 -2
2
4 -2
GHz-PLL
R2 R-Counter -----N2 N-Counter
1:1.51 tuning range

Possibilities of 2 band splitting without VCO at input frequency
Fvcomin Fvcomax Finmin Finmax Fvcomin Fvcomax Finmin Finmax 712 712 <- + -> 1076 1076 949 1424 <- + -> 1434 2152 700 1075 1400 2150 830 934 1245 1400 712 934 949 1245 1900 2870 1425 2152 2173 2867 1630 2150 <- + -> <- + -> 1900 2870 950 1435 1900 2910 950 1455
MHz MHz
R2 Fvco = ------ Fin N2 band switching at 1430 MHz
Possibilities of 3 band splitting without VCO at input frequency
2182 2445 1455 1630
1:1.53 tuning range
MHz R2 Fvco = ------ Fin N2 band switching at 1455, 1630 1245, 1400 MHz
MHz
low side VCO
VCO at Fin
high side VCO
Note: the maximum operating frequency of the synthesizer VCO is 2.9 GHz for the low side VCO mode and VCO at Fin application is not yet available.
8.11.3 Synthesizer VCO band switching
Programming tables of the synthesizer VCO band switching controlled by the GHz-PLL Register 01 Subaddress 01H
D23 0 1 GHz VCO Switch 3.4-6.2 GHz 6-8.6 GHz
Register 01 Subaddress 01H
N12 D21 0 0 1 1 N02 N-Counter D20 GHz-PLL 0 1 0 1 :3 :4 :2 :3
Register 02 Subaddress 02H
R12 D13 0 0 1 1 R02 R-Counter D12 GHz-PLL 0 1 0 1 :3 :4 :2 :3 RFin 2 band RFin 3 band 1455-1620 MHz
recommended switching at 1525 MHz RFin below 1525 MHz 0 3.4-6.2 GHz 1 1 0 0 0 0
recommended switching for band splitting (high side VCO), Fvco = 1900 - 2870 MHz 0 0 0 1 0 1 :2 :2 :3 :4 :3 :4 0 0 0 0 1 1 1 0 1 0 0 0 :4 :3 :4 :3 :2 :2
< 1430 MHz < 1455 MHz not used
RFin above 1525 MHz 1 6-8.6 GHz
> 1430 MHz > 1620 MHz < 1430 MHz < 1245 MHz not used 1245-1400 MHz
(low side VCO), Fvco = 712 - 1076 MHz
> 1430 MHz > 1400 MHz
The GHz VCO must be switched in any case at RFin =1525 MHz if a tuning range including frequencies below and above 1525 MHz is used.
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26.1.01
Preliminary Specification
TUA6100B6
8.12 Synthesizer PLL
Parameter see Synthesizer Phase detector Charge pump output / Loop filter input and Synthesizer PLL ( page 25). The PLL block forms a digitally programmable phase locked loop (PLL) with a serial bus control. The circuit consists of a serial control logic, a high frequency dual modulus prescaler, an A- and a N-counter with dual modulus control logic, a reference- (R-) counter, and a phase detector with lock detector and charge pump output.
8.12.1 Serial Bus Control Logic
For TUA6100 the combi-bus is selectable between I 2C and 3-wire-busmode by pin BUSMODE ( I2C = low, 3W = high ). All bus pins (CLOCK, DATA, ENABLE and BUSMODE) are Schmitt-triggered with input buffer for 3V or 5V C. Programming of the IC is done by a serial data protocol with sub addressing. The contents of the message is assigned to the functional units according to the preceded sub addresses. Before programming the counters the control register (sub address 00Hex) should be set. The data bit stream starts with the most significant bit (MSB) and is shifted in on the low to high transition of the clock signal.
* I2C bus mode
In this mode four different chip addresses can be set by appropriate DC level at pin ENABLE which has in this case the function of a chip address select (CAS). The pin DATA is a bidirectional input/output pin for serial data (SDA) from and the acknowledge bit (ACK) to the microcontroller (C). Data Transition: Data transition on the pin DATA must only occur when the serial clock (SCL) is low. SDA transitions while SCL is high will be interpreted as start or stop condition. Start Condition (STA): A start condition is defined by a high to low transition of the SDA line while SCL is at a stable high level.This start condition must precede any command and initiate a data transfer onto the bus. Stop Condition (STO): A stop condition is defined by a low to high transition of the SDA while the SCL line is at a stable high level. This condition terminate the communication between the devices and forces the bus interface into the initial conditions. Acknowledge (ACK): Indicates a successful data transfer. The transmitter will release the bus after sending 8 bit of data. During the 9th clock cycle the receiver will pull the SDA line to low level to indicate it has received the 8 bits of data correctly. Data Transfer Write Mode: To start the communication, the bus master must initiate a start condition, followed by the 8bit chip address (write). The chip address for the TUA 6100 is fixed as "11000xyz" (MSB at first). The last significant bit (LSB=z) of the chip address byte defines the type of operation to be performed: z=1 means, a read operation is selected and z=0 means, a write operation is selected. After the successful comparison of the transmitted chip address with the fixed one include the hard-switched chip address select bits CAS2=x and CAS1=y, the serial control logic of the TUA6100 will generate an ACK. Otherwise the processor must break off the data transfer. After this device addressing the desired subaddress byte and data bytes must be followed. The subaddresses determines which one of the data bytes (00H...03H) is transmitted first. At the end of the data transition the master must generate the stop condition.
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26.1.01
Preliminary Specification
TUA6100B6
Data Transfer Read Mode: To start the communication in the read mode, the bus master must initiate a start condition, followed by the 8bit chip address (write: z=0) and by the subaddress (80H) of the read register. Then followed by the chip address (read: z=1). After that procedure the 8bit data register 80H is read out. When the first byte(s) read out the C mandatory send LOW during the ACK-clock, but after the last byte is read out the C mandatory send HIGH (neg. ACK) during the ACK-clock. At the end of data transition the master must be generate the stop condition.
* 3-wire bus mode
Pin DATA is in this mode only data input. There is no data output. Pin ENABLE is used to activate the bus interface and to allow the transfer of data to the device. When ENABLE is in an inactive high state, shifting is inhibited. Data Transition: Data transition on the pin DATA must only occur when the clock SCL is low. To transfer data to the device, ENABLE (which must start inactive high) is taken low. A serial data transfer is made via DATA and CLOCK when ENABLE is taken back high. The bit stream doesn't need a chip address. Data Transfer Write Mode: To start the communication, the signal ENABLE is taken low. The desired subaddress byte and data bytes must be followed. The subaddresses determines which one of the data bytes (00H...03H) is transmitted first. At the end of the data transition the bus ENABLE must be high. Data Transfer Read Mode: To start the communication in the read mode, the ENABLE is taken low, followed by the subaddress read (xxH). After that the device is ready to read out the xbit data register xxH. At the end of the data transition the ENABLE must be high.
* Dual Modulus Prescaler
The dual modulus prescaler up to 2.5 GHz is switchable between divide ratio 32/33 and 64/65 by the bit D22 in the A/N-counter subaddress (01H). Input frequency of the prescaler is the divided GHz-VCO-frequency 4 with the range of 950 MHz .. 2150 MHz.
* R-Counter and A- / N-Counter
The TUA 6100 has a 10-bit counter for the R-path and a 7-bit and 11-bit counter for the A-/N-path. The input frequency for the R-counter is the buffered XTAL-frequency (1-16 MHz). Tuning steps can be selected by the programmable R-counter from fR = 31.25 kHz ..1 MHz (fXTAL=16MHz). The output frequency of the prescaler (14 MHz..70 MHz) passes the programmable dual modulus A-/N-counter which switches the prescaler and make available the comparison frequency fV for the digital frequency / phase detector.
* Phase Comparator (Frequency/Phase Detector)
The digital phase and frequency sensitive phase detector generates a phase error signal UP or DOWN according to the phase difference between fR (R-counter output) and fV (N-counter output). This phase error signal drives the charge pump current generator. Polarity is changeable via bus (bit D4 of the control register), it must be negative for TUA6100 application note. If the positive edge of the divided VCO signal appears prior to the positive edge of the reference signal, the DOWN-output pulses for the duration of the phase difference. In the reverse case the UP-output pulses. If the two signals are in phase (PLL is locked), the phase detector produces an output signal with fixed anti-backlash impulses in order to prevent a dead zone for very small phase deviations. Therefore phase differences of less than 100 ps can be resolved. In general the shortest anti-backlash pulse gives the best system performance.
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26.1.01
Preliminary Specification
TUA6100B6
* Charge Pump
The charge pump generates defined pulses of current (I+ and I-) by the phase detector UP- and DOWN signals. If the PLL is locked and the bit D1 of the control register is LOW, the charge pump output (pin 3: PDLOOP) goes into the high-impedance state. There are four current values selectable by bit D2 and D3 of the control register (subaddress 00H). Note : only 100A and 1mA are optimized. The synthesizer charge pump output may be disabled (high Z) by bus, control register(Register 00, D1).
* Lock Detector
The lock detector indicates when the PLL is locked (lock_in: LD_out = high). It is possible to put out the lock detect signal to the ports P0 or P2, by the control register bits D5 and D6. In this case the content of the respective control register bit for port P0 or P2 ( D18 of subaddress 01H or D10 of subaddress 02H ) is not active. Parallel the lock detector information may be read out by bus ( D7 of subaddress 80H ).
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26.1.01
High-Frequency-Products CAS / 13 26.1.01 rf fi =
8.12.2 Functional Synthesizer PLL Block Diagram
Charge Pump ri 10-Bit R-Counter Status Serial Control Logic CASDecoder
Iref I+ PD I-
fR fV Phase Detector
UP
Data Register
DOWN
Data Reg. Ctr. 2 CPext
Preliminary Specification
SCL / CLK SDA / DA
8-Bit Shift Register
8-Bit Shift Register
8-Bit Shift Register
LockDetector LD
Vcc GND
Data Register
Data Register
Data Reg. Ctr. 1
Port 0 (LD) Test mode 7-Bit A-Counter Prescaler 64 / 65 32 / 33 fi Dual Modulus Control 8-Bit Load SR 5-bit rf P / (P+1) VCO Switch 11-Bit N-Counter 4-bit Port 1 Port 2 (LD) Xtal out
TUA6100B6
Preliminary Specification
TUA6100B6
8.12.3 Divide ratio programming
Because of DCR concept the tuning frequency of the RF input controlled by the PLL is given below:
rf : ri : P: A: N: R: M = (PN)+A : Note :
frequency of RFinput reference frequency input (crystal oscillator) divide ratio of the prescaler [ P/(P+1) = (32/33) or (64/65) ] divide ratio of the A-counter (max. 7 bit) divide ratio of the N-counter (max. 11 bit) divide ratio of the R-counter (max. 10 bit) total divide ratio of the PLL (with A
P N +A

P
P-1
8.12.4 Phase detector outputs
fR fV
UP
Polarity (internal Signal) pos.
DOWN
Polarity (internal Signal) pos.
PD
Polarity pos.
P-Channel (I+) Tri-State. N-Channel (I-) P-Channel (I+) Tri-State. N-Channel (I-) Frequency fV < fR or fV lagging Frequency fV > fR or fV leading Frequency fV = fR (PLL is locked)
PD
Polarity neg.
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rf =
P N +A
ri M --- = ---- ri R R
with
A
N
26.1.01
Preliminary Specification
TUA6100B6
8.13 Bus Interface
Pin Function
Pin name
Function I C-mode (I2C)
2
BUSMODE Low
Data Data in / out Data in / out
Clock Clock Clock in
Enable Enable (3W) / Chip-Address-Select (I2C) Four Chip-Addresses (see below) High=Inactive, Low=Active
Bus-Mode-Select Serial data
3Wire mode (3W) High
8.13.1 Chipaddress Organisation
(only I2C-Mode) Chip Address MSB 1 1 1 1 0 0 0 0 0 0 CAS2 CAS1 CAS2 CAS1 LSB 0 1 Function Chip Address Write Chip Address Read
Chip-Address-Select (CAS) Voltage on Pin CAS1) 0...0,5 V open circuit 2,0..3,0 V > 4,5 How to do? Pin CAS external on GND Pin CAS = 1,25 V (intern) Rext = 68 kOhm external on Vcc , tolerance for R ext +-20% Pin CAS external on Vcc CAS2 CAS1 0 0 1 1 0 1 0 1 Chip-Address Hex C0 C2 C4 C6 Dec 192 194 196 198
1) Vcc = 5V, voltage is a function of resistor divider from Vcc
8.13.2 Subaddress Organisation
Sub Addresses of Write Data Registers
MSB 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 LSB Hex 0 1 0 1 0 00 01 02 03 80 Function Control-Register A/N-Counter R-Counter for future use Status-Register
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26.1.01
Preliminary Specification
TUA6100B6
8.13.3 Bus Data Format
I2C-bus write mode
Bit STA 1 1 0 0 0 CAS2 CAS1 0 ACK S7 S6 S5 S4 S3 S2 S1 S0 ACK DX ... D5 D4 D3 D2 D1 D0 ACK STO LSB MSB LSB MSB LSB MSB Function
I2C-bus read mode
Bit STA 1 1 0 0 0 CAS2 CAS1 0 ACK 1 0 0 0 0 0 0 0 ACK STA 1 1 0 0 0 CAS2 CAS1 1 ACK DX ... D5 D4 D3 D2 D1 D0 1 STO LSB MSB LSB restart MSB DX ... D5 D4 D3 D2 D1 D0 LSB MSB DX ... D5 D4 D3 D2 D1 D0 LSB MSB LSB MSB LSB MSB Function
CHIP ADDRESS (WRITE)
CHIP ADDRESS (WRITE)
3W-bus write mode
Bit S7 S6 S5 Function MSB
3W-bus read mode
Bit S7 S6 S5 S4 S3 S2 S1 S0 LSB Function MSB
SUB ADDRESS (WRITE) 00H...03H
SUB ADDRESS (READ) 80H
S4 S3 S2 S1 S0
SUB ADDRESS (WRITE) 00H...03H
SUB ADDRESS (READ) 80H
LSB
DATA_IN X...0 (X=7, 15 or 23)
CHIP ADDRESS (READ)
DATA_IN X...0 (X=7, 15 or 23)
DATA_OUT FROM SUB ADD X...0 (X=7)
DATA_OUT FROM SUB ADD X...0 (X=7)
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26.1.01
Preliminary Specification
TUA6100B6
8.13.4 Data Byte Specification
Register 00 Subaddress 00H Control - Register
Bit Function MSB Test-Mode / D7 Normal-Mode D6 D5 D4 D3 D2 D1 Test-Modes (in/out) LockDetect (on/off) LockDetect-Out on Port 0 / 2 Phase Detector polarity (+/-) ChargePump current 100/500A ,1/2mA Charge Pump (on/off)
Register 01 Subaddress 01H A/N-Counter,Ports,VCO
Bit Function MSB GHz VCO Switch D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 Prescaler Switch 32/33 <--> 64/65 N12 N02 Port 1 Port 0 2
0 1
Register 02 Subaddress 02H R-Counter,Ports,VCO
Bit Function MSB not used D15 (must be=0) D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 Base band amplifier disable R12 R02 R-Counter GHz-PLL
Register 03 Subaddress 03H for future use
Bit Function MSB D7 D6 D5 D4 D3 D2 D1 D0 LSB -
N-Counter GHz-PLL
not used Port 2 29 28 27 26 ratio of the 25 synthesizer 24 R-Counter 23 22 2 ....1023 21
D0 Loop filter OP LSB (on/off)
29 28 divide 27 26 24 2
3
divide
ratio of the
25 synthesizer N-Counter
Register 80 Subaddress 80H Status - Register (READ)
Bit Function
22 2 ....2047 21 20 26 25 23 22 divide
D0 20 LSB
MSB LockDetect-Out D7 D6 D5 D4 D3 D2 D1 D0 LSB for future use all bits high
24 ratio of the synthesizer
D3 D2 D1 D0 LSB
21 A-Counter 20 0 ....127
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26.1.01
Preliminary Specification
TUA6100B6
Control-Register (Register 00) ---> Subaddress 00H
Bit MSB D7 0 1 Test-Mode R-counter / 2 -> output to Port P0 N-counter / 2 -> output to Port P1 Port P0 -> input to R-counter Port P1 -> input to N-counter Bit D5 not active Bit D5 active LockDetect output on Port 0 LockDetect output on Port 2 PhaseDetector polarity negative PhaseDetector polarity positive Function Normal-Mode
Test-Mode:
It is possible to switch into an internal chip test mode by bit D7 of the control register (subaddress 00H). If test mode is activated there are two test options available by bit D6 of the control register: D6 = 0 --> Test-Mode1: In this case the output frequencies of the counters divided by 2 ( ! ) are put out to the Ports P0 ( R-counter output frequency / 2 ) and P1 ( N-counter output frequency / 2 ) Nevertheless the phase detector and the charge pump are in function ( lock detector = OFF ). D6 = 1 --> Test-Mode2: In this case the phase detector, charge pump and lock detector (= ON) can be tested by external frequencies which are applied to the Ports P0 (path of the R-counter frequency) and P1 (path of the N-counter frequency). ( Note: LD_out only on port P2 visible! )
D7 must be = 1 (Test-Mode) 0 D6 1
D7 must be = 0 (Normal-Mode) 0 1 D5 0 1 0 D4 1
D5 is only active for D6 = 1, D7 = 0
D3 D2 Synthesizer ChargePump current 0 D3 D2 0 1 1 D1 D0 LSB 0 1 0 1 0 1 0 1 100A 500A 1mA 2mA Synthesizer ChargePump disabled Synthesizer ChargePump enabled Synthesizer Loopfilter OP disabled Synthesizer Loopfilter OP enabled Bit MSB D7 D6 ..... D0 LSB
Status-Register (READ) (Register 128) ---> Subaddress 80H
Function 0 1 1 1 1 for future use, all bits = 1 synthesizer PLL unlocked synthesizer PLL locked
Prescaler, Ports, GHz-PLL (Register 01) ---> Subaddress 01H
Bit MSB D23 D22 D21 0 D21 D20 0 1 1 D19 D18 0 1 0 1 0 1 0 1 D20 0 1 0 1 Function GHz VCO = 3.4-6.2 GHz GHz VCO = 6-8.6 GHz Prescaler divide ratio 32/33 Prescaler divide ratio 64/65 N-Counter GHz-PLL :3 :4 :2 :3 Port_1 output = low level Port_1 output = high level Port_0 output = low level Port_0 output = high level 18 D11 D10 D13 D12 MSB D15 D14
Ports, GHz-PLL (Register 02) ---> Subaddress 02H
Bit 0 0 1 D13 0 0 1 1 0 1 0 1 D12 0 1 0 1 Port_2 output = low level Port_2 output = high level 26.1.01 Function not used (must be=0) base band amplifier enabled base band amplifier disabled R-Counter GHz-PLL :3 :4 :2 :3
High-Frequency-Products
Preliminary Specification
TUA6100B6
8.13.5 Bus Timing
I2C Bus
BUS_MODE = LOW tBUF SDA tLOW tR SCL P S tHD.STA tHD.DAT tHIGH tSU.DAT tHD.STA S tSU.STA tSU.STO P tF tSP
CAS (ENABLE) tSU.ENASDA tSU.ENASDA S - START condition P - STOP condition tSU.ENASDA
3W-Bus
BUS_MODE = HIGH
DATA tLOW tR CLOCK tWHEN ENABLE S tSU.SCLENA P tSU.SCLENA tHD.STA tHD.DAT tHIGH tSU.DAT tSU.STO tF tSP
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26.1.01
Preliminary Specification
TUA6100B6
Parameter see also I2C and 3-Wire-bus on page 26
LOW level input voltage (DATA, CLOCK, ENABLE, BUS_MODE) HIGH level input voltage (DATA, CLOCK, ENABLE, BUS_MODE) Hysteresis of Schmitt trigger inputs Pulse width of spikes which must be suppressed by the input filter LOW level output voltage (DATA), only I2C-bus at 3mA sink current at 6mA sink current Output fall time from VIH min to VIL max with a bus capacitance from 10pF to 400pF with up to 3mA sink current at VOL SCL clock frequency Bus free time between a STOP and START condition Hold time (repeated) START condition. After this period, the first clock pulse is generated. 2) LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition 2) Data hold time Data set-up time Rise time, fall time of SDA and SCL signals Set-up time for STOP condition 2) Setup time BUS_ENA to SDA 2) Setup time CLOCK to BUS_ENA Capacitive load for each bus line
3) 2)
Symbol
VIL VIH VHys tSP
Limit Values
min. -0.5 2.24 max. 0.96 5.5 1.12 0 50
Unit
V V V ns
VOL tOF
0
0.4 0.6
V
20+0.1C b1) 250
ns
fSCL tBUF tHD.STA tLOW tHIGH tSU.STA tHD.DAT tSU.DAT tR, tF tSU.STO
0 1.3 0.6 1.3 0.6 0.6 0 100 0.6
400 ----------400
kHz s s s s s ns ns ns s s s s pF
20+0.1C b1) 300
tSU.ENASDA 0.6 tSU.SCLENA 0.6 tWHEN Cb 0.6 --
H-pulse width (BUS_ENA) for new data protocol 3)
1) Cb= capacitance of one bus line in pF Note that the maximum tF for the SDA and SCL bus lines quoted in table above (300ns) is longer than the specified maximum tOF for the output stages (250ns).This allows series protection resistors to be connected between the SDA/SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tF . 2) only for I2C bus mode 3) only for I2C bus mode
High-Frequency-Products
20
26.1.01
Preliminary Specification
TUA6100B6
9
Electrical Characteristics
9.1 Absolute Maximum Ratings
The maximal ratings may not be exceeded under any circumstances, not even momentary and individual, as permanent damage to the IC will result.
Parameter
Supply voltage Supply voltage 1 Crystal oscillator Crystal oscillator buffered output Synthesizer Charge pump out Loop filter in Synthesizer Loop filter tuning output VCO inputs Port outputs Port outputs , VP0,P1,P2 = VVCC, I=max GHz-PLL Charge pump out Baseband outputs I / Q Baseband filtered inputs I / Q Baseband filtered Output I / Q AGC voltage RF input I2C / 3-Wire-Bus
Symbol
VVCC VVCC1 VQOSZ VXTALOUT VPDLOOP VTUNE VOB1,VOB2 VP0,P1,P2 IP0,P1,P2 IP0,P1,P2
Limit Values
min. - 0.3 - 0.3 VVCC-3 > 0 0 0 - 0.3 0 0 max. 5.5 5.5 VVCC-1 > 0 VVCC VVCC 35 VVCC VVCC 15 30 1 0 0 0 0 0 0 VVCC VVCC1 4 VVCC1 VVCC1 4 VVCC1 1.5 < VVCC1 VVCC+0.3
Units
V V V V V V V V mA mA ms V V mA V V mA V V V
t Imax VPDOUT VIOUT , QOUT IIOUT , QOUT VIFIN,VQFIN VIFOUT , QFOUT IIFOUT , QFOUT VAGC VRFINX , RFINY
SCL, SDA,CAS - 0.3 BUSMODE
All values are referred to ground (pin), unless stated otherwise. All currents are designated according to the source and sink principle, i.e. if the device pin is to be regarded as a sink (the current flows into the stated pin to internal ground), it has a negative sign, and if it is a source (the current flows from Vs across the designated pin), it has a positive sign.
High-Frequency-Products
21
26.1.01
Preliminary Specification
TUA6100B6
Parameter Absolute Maximum Ratings continued
ESD-Protection pin 4, Tune 1) ESD-Protection all other bipolar pins 1) ESD-Protection all CMOS pins 1) Total power dissipation Ambient temperature Junction temperature Storage temperature Thermal resistance junction case
Symbol
Limit Values
min. - 500 -1 -1 - 20 - 40 max. 500 1 1 687.5 see note 125 150 2
Units
VESD VESD VESD Ptot TA Tj Tstg Rth
V kV kV mW C 2) C C K/W
1) all ESD tests done according to EIA/JESD22-A114-B (HBM incircuit test), as a single device incircuit contact discharge test. 2) The maximum ambient temperature dependends on the mounting conditions of the package. Any application mounting must guarantee not to exceed the maximum junction temperature of 125 C. As reference the thermal resistance junction to case is given. To reach a high ambient temperature, a good solution is a 2-layer PCB board with complete GND plane under the chip body and a 2nd complete layer ground plane. Additional the area under the chip body should be equipped with as many via holes as possible, solded to the 2nd layer. Not used pins should be solded to GND if possible (e.g. unused ports).
9.2 Operating Range
Within the operational range the IC operates as described in the circuit description. The AC / DC characteristic limits are not guaranteed.
Parameter
Supply voltage Supply voltage 1 Difference between VCC...VCC1 and between GND...GND1 Current consumption Input frequency range of mixer VCO frequency range Synthesizer Loop filter tuning output Ambient temperature
Symbol
VVCC VVCC1 V
Limit Values
min 4.5 4.5 -0.3 max 5.5 5.5 0.3 125 950 0.7 0.5 - 20 2150 3 33 see note
Unit
V V V mA MHz GHz V C 2)
Test Conditions
Ivcc+vcc1 fRFIN fVCO VTUNE TA
High-Frequency-Products
22
26.1.01
Preliminary Specification
TUA6100B6
9.3 AC/DC Characteristics
AC / DC characteristics involve the spread of values guaranteed in the specified supply voltage and ambient temperature range. Typical characteristics are the median of the production.
Parameter
TA = 25 C,VVCC, VVCC1 = 5V
Power supply
Total current consumption
Symbol
Limit Values
min typ max
Unit
Test conditions
IVCC+IVCC1
110
125
mA
RL>1M,C L<1.5pf
Input frequency minimum input RF level maximum input RF level Input impedance differential without any application Input gain control range Internal mixer gain VCO power present at RF input LO power present at RF input input compression point -1 dB output compression point -1 dB Input IP2 Input IP3 Output IP3 Noise Figure @1400 MHz
fRFIN VRFIN VRFIN R RFIN LRFIN A A
950 -55 15 1.3 40 -10 - 60 - 74 -7 + 13 + 28 +1 + 21 -5 + 15 + 32 +5 + 25 15 43
45 30 - 50 - 70
dBm dBm dBm dBm dBm dBm
F
16
dB
Base band I / Q output, IOUT, QOUT, pin 19, 20 (see Baseband Amplifier on page 5)
DC voltage DC quiescent current Baseband I/Q output voltage Baseband I/Q output bandwidth both amplifiers in series see diagrams 13.1 and 13.3 Baseband I/Q output flatness Quadrature error, phase Quadrature error, gain Internal amplifier gain Baseband I/Q output impedance VIOUT VQOUT IIOUT,IQOUT VIOUT VQOUT f -0.1 dB f -1 dB

2.15 2.7 225 25 35 70 0.05 1 1 16 50 0.1 3 2.5 1000
A R IOUT, R QOUT
High-Frequency-Products
23
RF input (950-2150MHz) symm. balanced signal (see Input Mixer on page 5) RF source impedance 50
balanced input, test circuit see page 27 2150 -50 -15 MHz dBm dBm balanced balanced 1100 MHz balanced 1100 MHz f = 0.9 - 2.2 GHz see diagrams 13.5 and page 38 VGAIN=0.4...2.6V see diagrams 13.4 f = R2 / N2 x fin f = fin minimum gain minimum gain,Vcc=5V minimum gain minimum gain minimum gain maximum gain, SSB
n dB dB dBm

V mA mV pp MHz MHz dB deg dB dB
RL>1M RL>1M RL>1M no filter, IOUT-IFIN 47nF QOUT-QFIN 47nF up to 25 MHz balanced @ 1100 MHz RFin= -35 dBm, test circuit see page 27 internal from mixer output to I / Q OUT dynamic resistance
26.1.01
Preliminary Specification
TUA6100B6
Parameter
TA = 25 C,VVCC, VVCC1 = 5V
Symbol
Limit Values
min typ max
Unit
Test conditions
I / Q base band filtered input signal IFIN, QFIN, pin 15, 17 (see Baseband Amplifier on page 5)
DC voltage Baseband I/Q input impedance VIFIN,V QFIN R IFIN,QFIN 2.1 18 V k see filter on page 33 see diagrams 13.8
Base band I / Q output filtered, IFOUT, QFOUT, pin 13, 14 (see Baseband Amplifier on page 5) symm. balanced input application
DC voltage DC quiescent current Baseband I/Q output voltage Base band I/Q output bandwidth both amplifiers in series see diagrams 13.1 and 13.3 Amplifier gain Group delay variation, see 13.2 both amplifiers in series Baseband I/Q output impedance S/N @ 45 Mbaud S/N @ 45 Mbaud VIFOUT VQFOUT IIFOUT IQFOUT VIFOUT VQFOUT f - 0.5 dB f - 1 dB A t
2.1 2.7 1 20 27 22 30 16 -250 250 50 24 30 26 32 3.5
V mA Vpp MHz MHz dB ps
RL>1M RL>1M RL>1M no filter,15pf/1k load IOUT-IFIN 47nF QOUT-QFIN 47nF VI,QFOUT / VI,QFIN 100kHz ..... 100MHz dynamic resistance maximum gain, 1Vpp minimum gain, 1Vpp
R IFOUT, R QFOUT
IFOUT,QFOUT IFOUT,QFOUT
dB dB
AGC voltage input (see Input Mixer on page 5)
Gain control input impedance Gain control input clamp voltage Gain control input clamp current R GAIN VGAINmax IGAINmax
Gain control range
VGAIN
0.4 100 100e 3.75 180
6
2.6
V
see diagrams 13.4 protected by resistor VGAIN = Vcc1
V

500
A
Synthesizer Phase detector Charge pump output / Loop filter input (see Synthesizer Loop filter on page 6)
DC voltage DC current Tristate output current VPDLOOP IPDLOOP IPDLOOP 0.1 0.1 1.8 2 1 V mA nA locked see Control-Register VPDLOOP = 2 V , guaranteed by design
Reference oscillator input / Crystal (see Reference Oscillator on page 5)
DC voltage Crystal frequency Crystal resistance negative input impedance Drive current VQOSZ f f ZQOSZ IQOSZ 1 10 - 500 - 700 135 3.4 4 16 100 - 900 V MHz

series resonance series resonance f = 4 MHz
Arms f = 16 MHz, Cs=18pF
High-Frequency-Products
24
26.1.01
Preliminary Specification
TUA6100B6
Parameter
TA = 25 C,VVCC, VVCC1 = 5V
Symbol
Limit Values
min typ max
Unit
Test conditions
Synthesizer Loop filter high voltage tuning output (see Synthesizer Loop filter on page 6)
LOW output voltage HIGH output current VTUNE ITUNE 0 0 0.5 10 V A
ITUNE = 1.5 mA VTUNE = 33V
Synthesizer PLL (see Synthesizer PLL on page 10)
N-counter divide ratio A-counter divide ratio R-counter divide ratio P-counter divide ratio Equivalent phase noise at phase detector input, @ 1 kHz offset, within loop band width, 6 kHz loop BW, SSB Quadrature phase mismatch Total divide ratio see see 8.12.3 on page 14 PLL tuning step size (programmable via R-counter) see Register 02 Continuous step size see 8.12.3 (programmable via R-counter) Continuous step size see 8.12.3 (programmable via R-counter) Frequency range with continuous step size for P = 32/33
1)
N A R P
2 0 2 32/33 -164 -159 -158 -155 -149 1 992 4032 0.9775 3.91 125 15.650 32.759 16.395 950 950 950 992 1984 950 950 1008 2016 6 24 96
2047 127 1023 64/65
dBc / Hz dBc /Hz dBc /Hz dBc / Hz dBc /Hz
11-Bit, CMOS 7- Bit, CMOS 10-Bit, CMOS 5/6-Bit, Bipolar Fref = 30 kHz Fref = 100 kHz Fref = 125 kHz Fref = 250 kHz Fref = 1000 kHz P=32/33 P=64/65 kHz f crystal = 1 MHz f crystal = 4 MHz f crystal = 16 MHz P = 32/33 f in = 950 - 2150 MHz P = 64/65 f in = 950 - 2150 MHz fref = 15.625 kHz fref = 31.250 kHz fref = 62.5 ...500 kHz fref = 1.000 MHz fref = 2.000 MHz fref = 15.625 kHz fref = 31.25...166.7 kHz fref = 250 kHz fref = 500 kHz f crystal = 1 MHz f crystal = 4 MHz f crystal = 16 MHz
3 65.631 131.135 500 2000 8000 2) 957.66 235.61 1025 2050 2150 2150 2150 2048 2150 2150 2150
deg
fref fref
f
Frequency range with continuous step size for P = 64/65 3) R-counter values for 166.666 kHz step size
1)
R
The minimum total divide ratio is only important for continuous frequency step size, if lower divide ratios are used not all frequencies are possible. To find out the missing frequencies our Windows control program for I2C / 3-wire bus may be used. 2) Step sizes > 2 MHz are not guaranteed, 1 MHz continuous step size is only possible for RFin > 992 MHz 3) For low power dissipation the use of the 64/65 prescaler should be preferred if the desired step size fits
High-Frequency-Products

M
fref
kHz kHz
MHz
f
MHz
25
26.1.01
Preliminary Specification
TUA6100B6
Parameter
TA = 25 C,VVCC, VVCC1 = 5V
Synthesizer VCO (see Synthesizer VCO on page 6)
DC voltage high side VCO frequency range high side VCO frequency range low side VCO frequency range low side VCO frequency range high side VCO frequency range low side VCO frequency range Phase noise high side VCO1)
1) 1)
Symbol
Limit Values
min typ max
Unit
Test conditions
VOB1,VOB2 fVCO fVCO fVCO fVCO fVCO fVCO 1900 1900 712 700 1424 950 - 53 - 73 - 93
1.9 2870 2910 1076 1075 2151 1434 - 56 - 76 - 96 - 60 - 80 - 100
V MHz MHz MHz MHz MHz MHz dBc dBc dBc 2 band split, page 32 3 band split, page 32 2 band split, page 32 3 band split, page 32 +VCO at fin, band split +VCO at fin, band split 1 kHz offset, SSB 10 kHz offset, SSB 100 kHz offset, SSB
Phase noise high side VCO Phase noise high side VCO
1)
Note : This is the phase noise of the free running VCO, not for the overall system performance at baseband output. For detailed system phase noise information see diagrams page 30 and page 31 and our separate application note.
Port outputs, P0, P1, P2 (see Output Ports on page 5)
Supply voltage LOW output voltage LOW output current HIGH output current Port outputs, I=max VP VP IP IP t Imax 0 0 0 5.5 0.5 15 10 1 V V mA A VP = 5 V VP0,P1,P2=VVCC
max. Vcc IP = 15 mA
ms
Crystal oscillator output (see Crystal Oscillator Output on page 6)
Buffer output voltage 1) Buffer output current Buffer output impedance VXtalout IXtalout R Xtalout 350 1.1 1 Vpp mA
RL>1M Vcc=5V, CL = 10 pF, f = 16 MHz
I2C and 3-Wire-bus Clock, Data, Enable, BUS_MODE (see Bus Data Format on page 16 and 8.13.5 Bus Timing on page 19)
HIGH level input voltage LOW level input voltage LOW level output voltage (DATA), only I2C-bus VIH VIL VOL 2.24 -0.5 0 0.2 -60 5 1 10 VVCC 0.96 0.4 0.6 V V V V A A VI = VVCC = 5.5V VI = GND
3mA sink current 6mA sink current
Hysteresis of Schmitt trigger inputs Vhys H-input current IH L-input current Input capacity
1) output voltage is dependant on Vcc
CI
High-Frequency-Products
26
IL
pF
26.1.01
High-Frequency-Products 27 26.1.01
10 Test circuit
100pF
100pF
100
100pF
+ 5V P0
RF
6.8pF 6.8pF
Gain
4.7nF 4.7nF 2.2k 4.7nF
Bus Control CAS
SCL Xtalout
SDA
100
100
+ 5V
10pF
10pF
3.3k
825
825
28
27
26
25
24
23
22
21
20
19
18
17
16
15
digital power supply Buffer Ports
Dual I /Q Mixer -10..30 dB Gain
Dual 16 dB Baseband Amplifier Dual 16 dB Baseband Amplifier
Preliminary Specification
Wide band Loop Filter 25 kHz
CMOS Synthesizer PLL GHz Prescaler GHz PLL (4 x Fin) Quadratur Phase Generator Loop Synthesizer VCO
Power Regulation
Tuning Crystal Oscillator Active Loopfilter
Low Noise Bandgap
analog power supply
1 18pF
2
3
4
5
6 12pF
7
8 12pF
9
10
100pF
11
12 147
13
14 147
4.7k 16 MHz
3.3k
4.7k 1nF 5.6k 5.6k BB857 BB857 4.7k 1.2nF
3.3k
1nF 100k
TUA6100B6
+ 5V
100nF 33k
1nF
+ 5V P1
100k
P2 + 5V
I
Q
+ 33V
High-Frequency-Products 28 26.1.01
* high side synthesizer VCO narrow band loop filter example
11 Application circuits
3 kHz typ.
RF
100pF 100pF
100
100pF
+ 5V P0
3.9pF
10
3.9pF
Gain
47nF 47nF 4.7nF 150 150 39pF 39pF
Bus Control CAS
SCL Xtalout
10pF
SDA
100
100
l=min. 5mm d=0.65mm 4.7k 4.7nF
+ 5V
4.7pF
1H
22pF
22pF
1H
4.7pF
28
27
26
25
24
23
22
21
20
19
18
17
16
15
digital power supply Buffer Ports
Narrow band Loop Filter 3 kHz
CMOS Synthesizer PLL GHz Prescaler
Dual I /Q Mixer -10..30 dB Gain
Dual 16 dB Baseband Amplifier Dual 16 dB Baseband Amplifier
Preliminary Specification
GHz PLL (4 x Fin) Quadratur Phase Generator Loop Synthesizer VCO
Power Regulation
Tuning Crystal Oscillator Active Loopfilter
Low Noise Bandgap
analog power supply
1 18pF
2
3 1nF
4
5
6 12pF
7
8 12pF
9
10 4.7k
11
12
13
14
4.7k 4 MHz
1nF
1k
1k
+ 5V
220nF 33k
2.2k 4.7nF BB835 BB835 10k
2.2k
TUA6100B6
I
Q
+ 33V
4.7nF
High-Frequency-Products 29 26.1.01
* high side synthesizer VCO wide band loop filter example
25 kHz typ.
RF
100pF 100pF
100
100pF
+ 5V P0
3.9pF
10
3.9pF
Gain
47nF 47nF 4.7nF 150 150 39pF 39pF
Bus Control CAS
SCL Xtalout
10pF
SDA
100
100
l=min. 5mm d=0.65mm 4.7k 4.7nF
+ 5V
4.7pF
1H
22pF
22pF
1H
4.7pF
28
27
26
25
24
23
22
21
20
19
18
17
16
15
digital power supply Buffer Ports
Dual I /Q Mixer -10..30 dB Gain
Wide band Loop Filter 25 kHz
CMOS Synthesizer PLL GHz Prescaler GHz PLL (4 x Fin) Quadratur Phase Generator Loop Synthesizer VCO
Dual 16 dB Baseband Amplifier
Dual 16 dB Baseband Amplifier
Preliminary Specification
Power Regulation
Tuning Crystal Oscillator Active Loopfilter
Low Noise Bandgap
analog power supply
1 18pF
2
3
4
5
6 12pF
7
8 12pF
9
10 4.7k
11
12
13
14
4.7k 16 MHz
1nF
1k
1k
+ 5V
100nF 33k
2.2k BB835 BB835 4.7k
2.2k
TUA6100B6
I
Q
+ 33V
1.2nF
Preliminary Specification
TUA6100B6
* Phase noise performance of application
The over all system phase noise at base band of the TUA 6100 is strongly dependent on several parameter : 1.programming of the 2nd PLL (GHz-PLL setting of the R2 and N2 counter) 2.programming of the 1st synthesizer PLL - receiving frequency (variation of the VCO steepness due to non linearity of the varicap), - phase detector current, - crystal frequency, - step size = Fref, - loop filter parameter. ( bandwidth ) A well balanced phase noise over the whole tuning range requires an optimized parameter programming of the synthesizer PLL for each receiving frequency - 1st you have to decide for the optimum loop filter bandwidth for your application. Narrow band loop filter : achieves better PLL outband phase noise at high frequencies offset but lower PLL inband phase noise at low frequency offset. Wide band loop filter : achieves better PLL inband phase noise at low frequencies offset but lower PLL outband phase noise at high frequency offset. - 2nd you have to decide for the crystal frequency for your application. Higher crystal frequency achieves better PLL inband phase noise. - 3rd you have to decide for the varicap for your application. Linear varicaps achieves better balanced phase noise than non linear varicaps. - 4th you have to decide for the main stepsize for your application. Higher step size achieve better PLL inband phase noise. - 5th during programming the desired receiving frequency you have to set step size and phase detector output current for each frequency. This is necessary to compensate the non linearity of the varicap.
All this is done in our separate application note with the above two application circuits which obtain the following worst case phase noise values :
Narrow band loop filter Offset Frequency Measured phase noise at base band Wide band loop filter Offset Frequency Measured phase noise at base band 3 1 - 55 30 1 - 75 3 10 - 76 30 10 - 77 3 100 - 98 30 100 - 91 3 1000 - 100 30 1000 - 100 kHz kHz dBc/Hz kHz kHz dBc/Hz
For detailed information see our separate application note version B5.
High-Frequency-Products
30
26.1.01
Preliminary Specification
TUA6100B6
.
* Optimum phase detector current
valid for the two applications above, band splitting into 2 ranges
Optimum Chargepump current for constant loop bandwidth and phasenoise
3,0 2,8
available current of TUA 6100
2,6
low band (ratio 2) high band (ratio 4/3)
border between 2 currents
2,4 2,2 2,0 1,8 1,6 1,4 1,2 1,0 0,8 0,6 0,4 0,2 0,0 950
1050
1150
1250
1350
1450
1550
1650
1750
1850
1950
2050
2150
Fin [MHz]
* VCO steepness + phase detector current ranges
valid for the two applications above, band splitting into 2 ranges
Kvco
200
180 Ratio=2 Ratio=4/3 160
140
120
MHz / V
100
80
60
40
0.5mA 1mA 2mA 0.5mA
1mA 1750 1850 1950
2mA
20 950
1050
1150
1250
1350
1450
1550
1650
2050
2150
Finput [MHz]
High-Frequency-Products
31
26.1.01
Preliminary Specification
TUA6100B6
* VCO tuning voltage
valid for the two applications above, band splitting into 2 ranges
F input 2200 2100 2000 1900
Ratio=4/3
1800 1700
Ratio=2
[MHz]
1600 1500 1400 1300 1200 1100 1000 900 2 3 4 5 6 7 8 9 10 Tuning Voltage [V] 11 12 13 14 15
* Receiving frequency band splitting into 2 or 3 ranges
3 band programming reduces the VCO pulling in the frequency range from 1430 to 1630 MHz
high side VCO splitting , 2 + 3 ranges
2900 2800
VCO frequency range
2700 2600 2500 2400 2300
vco 2 ranges vco 3 ranges
Fvco [MHz]
R2/N2 =4/2 =2.0
R2/N2 = 3/2 = 1.5
R2/N2 = 4/3 = 1.333
1455
2200 2100 2000 1900 900
1630 Receiving frequency range
1430
1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200
Finput [MHz]
High-Frequency-Products
32
26.1.01
Preliminary Specification
TUA6100B6
12 Base band filter
for 45 MBaud signals
BW = 25 MHz -1dB
Baseband amplifier
from mixer
150
47nF
4.7pF
Baseband amplifier
Baseband output 15pF 1k parasitic
. .
+16dB
TUA 6100 internal 22pF
1H
39pF
. .
+16dB
TUA 6100 internal
* Frequency response incl. the two base band amplifiers + output load
40.0
fLow: 25.258meg -1dB 30.0
20.0
fLow: 30.676meg -3dB
10.0 dB(V)
fLow: 47.546meg -20dB
0.0
fLow: 56.469meg -30dB
-10.0
fLow: 63.302meg -40dB
fLow: 67.177meg -50dB -20.0
-30.0 2meg 3meg 5meg 7meg 10meg 20meg f(Hz) 30meg 50meg 70meg 100meg 200meg
* Group delay incl. the two +16 dB base band amplifiers + output load
4n
3n group delay (s)
2n
1n
0.0
-1n 2meg 3meg 5meg 7meg 10meg 20meg f(Hz) 30meg 50meg 70meg 100meg 200meg
High-Frequency-Products
33
26.1.01
Preliminary Specification
TUA6100B6
13 Electrical Diagrams
13.1 Frequency flatness of base band outputs
without base band filter, both base band amplifiers in series, coupling capacitor 47nF
32.0 31.8 31.6 31.4 31.2 31.0 30.8 30.6 30.4 30.2 dB(V) 30.0 29.8 29.6 29.4 29.2 29.0 28.8 28.6 28.4 28.2 28.0 100.0k 200.0k 500.0k 1meg 2meg f(Hz) 5meg 10meg 20meg 50meg 100meg (50.034meg, 28.617) Delta Y: -2.7339 (40.007meg, 29.511) Delta Y: -1.8355 (30.076meg, 30.278) Delta Y: -1.068 (20.033meg, 30.872) Delta Y: -0.47584
13.2 Group delay of base band outputs
without base band filter, both base band amplifiers in series, coupling capacitor 47nF
0.0 -10p -20p -30p -40p -50p -60p -70p -80p -90p -100p -110p -120p -130p -140p -150p 100.0k 200.0k 500.0k 1meg 2meg f(Hz) 5meg 10meg 20meg 50meg 100meg
High-Frequency-Products
group delay (s)
34
26.1.01
Preliminary Specification
TUA6100B6
13.3 Frequency response of base band outputs
without base band filter, both base band amplifiers in series, coupling capacitor 47nF
35.0
30.0 fHigh: 371.24 -1dB 25.0 fHigh: 189.23 -3dB 20.0 fLow: 29.503meg -1dB fLow: 53.587meg -3dB
15.0
10.0
dB(V)
5.0
0.0
-5.0
-10.0
-15.0
-20.0 1.0 3.0 10.0 30.0 100.0 0.3k 1.0k 3.0k 10.0k 30.0k f(Hz) 100.0k 300.0k 1meg 3meg 10meg 30meg 100meg 300meg 1g
Group delay (coupling capacitor 47nF, low frequencies response is dependent on coupling capacitor)
0.0 -2u -4u -6u -8u -10u -12u -14u -16u 1.0 3.0 10.0 30.0 100.0 0.3k 1.0k 3.0k 10.0k 30.0k f(Hz) 100.0k 300.0k 1meg 3meg 10meg 30meg 100meg 300meg 1g
grop delay (s) grop delay (s)
0.0
-20n
-40n
-60n 1.0 3.0 10.0 30.0 100.0 0.3k 1.0k 3.0k 10.0k 30.0k f(Hz) 100.0k 300.0k 1meg 3meg 10meg 30meg 100meg 300meg 1g
0.0 -20p -40p -60p -80p -100p -120p -140p -160p 1.0 3.0 10.0 30.0 100.0 0.3k 1.0k 3.0k 10.0k 30.0k f(Hz) 100.0k 300.0k 1meg 3meg 10meg 30meg 100meg 300meg 1g
High-Frequency-Products
grop delay (s)
35
26.1.01
Preliminary Specification
TUA6100B6
*
Group delay at low frequencies, dependent on coupling capacitor
Group delay versus coupling condensator at low frequencies 0.0
-20n
CK=4700nF
CK=470nF
CK=47nF
CK=4.7nF
-40n
-60n group delay (s)
-80n
-100n
-120n
-140n
-160n 100.0 0.2k 0.5k 1.0k 2.0k 5.0k 10.0k f(Hz) 20.0k 50.0k 100.0k 200.0k 500.0k 1meg
13.4 RF gain control range
64.0 62.0 60.0 58.0 56.0 54.0 52.0 50.0 48.0 46.0 gain variation (dB) 44.0 42.0 40.0 38.0 36.0 34.0 32.0 30.0 28.0 26.0 24.0 22.0 20.0 18.0 16.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 gain control voltage (V) 1.8 2.0 2.2 2.4 2.6 2.8 3.0
High-Frequency-Products
36
26.1.01
Preliminary Specification
TUA6100B6
13.5 RF input impedance
18.5
18.0
17.5 Input resistance (Ohm)
17.0
16.5
16.0
15.5 800meg 1g 1.2g 1.4g 1.6g 1.8g f(Hz) 2g 2.2g 2.4g 2.6g 2.8g 3g
1.37n
1.36n
1.35n
1.34n Input Inductance (H)
1.33n
1.32n
1.31n
1.3n
1.29n 800meg 1g 1.2g 1.4g 1.6g 1.8g f(Hz) 2g 2.2g 2.4g 2.6g 2.8g 3g
High-Frequency-Products
37
26.1.01
Preliminary Specification
TUA6100B6
* RF input impedance continued, Smith diagram
40
35
45
50
30
75
25
10
0
100
150
200
250
500
10
15
20
25
30
35
40 45 50
75
0
1k
200
5
15
20
25 10 0 15 0
30
35
40
45
13.6 Base band output impedance pin 13, 14 (filtered), Smith diagram
identical to pin 19, 20
100
40
50
90
45
50
80
110
35
30
70
60
10
120
75
75
1 0
20
25
30
50 40
14
0
15
0
150
160
100 M
170
30 M
100 150 200 250 500 10 15 20 25 30 35 40 45 50 75
180
0
1k
5
1M
5
1k
-170
-160
0 -15
15
40
20
-1
25
10
0
30
35
40
45
50
High-Frequency-Products
38
75
250
10
500
250
10
250
500
5
500
1k
1k
200
200
15
0
-5
0
-60
-70
-80
-90
-100
-110
-
120
-1
30
20
15 0
200
15
3 GHz 2 GHz 1 GHz 800 MHz
250
15
10 10
500
1k
5 5
30
20
10
0
-10
-20
-30
-4 0
26.1.01
Preliminary Specification
TUA6100B6
13.7 Base band output impedance pin 19, 20 , Smith diagram
110
35
30
40
45
50
100
90
80
70
60
10
120
75
1 0
20
25
30
50 40
14
0
15
0
200
150
160
170
30 M
100 150 200 250 500 10 15 20 25 30 35 40 45 50 75
180
0
1k
5
1M
5
1k
-170
-160
0 -15
15
40
20
-1
25
10
0
30
35
40
45
50
*
Base band output impedance Pin 19, 20 (Ohm)
12.0
11.0
10.0
9.0
8.0
7.0
Ohm
6.0
5.0
4.0
3.0
2.0
1.0
0.0 100.0k 200.0k 300.0k 600.0k 1meg 2meg 3meg f(Hz) 6meg 10meg 20meg 30meg 60meg 100meg
High-Frequency-Products
39
75
250
10
500
200
15
0
-5
0
-60
-70
-80
-90
-100
-110
-12 0
-1
30
15
30
250
10
20
100 M
500
1k
10
5
0
-10
-20
-30
-4 0
26.1.01
Preliminary Specification
TUA6100B6
*
Base band output inductance Pin 19, 20 (Henry)
35n
30n
Henry
25n
20n
15n 100.0k 200.0k 300.0k 600.0k 1meg 2meg 3meg f(Hz) 6meg 10meg 20meg 30meg 60meg 100meg
13.8 Base band Input Impedance (filtered)
50
35
40
45
30
75
25
10
0
100
150
200
250
500
10
15
20
25
30
35
40 45 50
75
0
100 MHz
500 5
1k
15
20
0 10 25 15 0
30
35
40
45
High-Frequency-Products
50
40
75
250
10
1k
5
200
20
15 0
200
15
250 10
500
1k
5
0 MHz
26.1.01
Preliminary Specification
TUA6100B6
14 Package Outlines
Plastic Package, P-TSSOP-28-1 alloy leadframe (Plastic Thin Shrink Small Outline)
Plastic Package, P-TSSOP-28-5 copper leadframe (Plastic Thin Shrink Small Outline)
High-Frequency-Products
0.9
41
26.1.01

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